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spoc - BTS5566G spi power controller data sheet, rev. 1.3, october 2007 automotive power
data sheet 2 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 pin assignment spoc - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 power supply modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7protectionfunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6 loss of v bb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.8 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 diagnosis word at spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 load current sense diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 switch bypass diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.5 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.6 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 package outlines spoc - BTS5566G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table of contents
pg-dso-36-34 type package marking spoc - BTS5566G pg-dso-36-34 BTS5566G data sheet 3 rev. 1.3, 2007-10-30 spi power controller for advanced light control spoc - BTS5566G 1overview the spoc - BTS5566G is a five channel high-side smart power switch in pg-dso-36-34 package providing embedded protective functions. it is especially designed to control stan dard exterior lighting in automotive applications. it is designed to drive lamps up to 3*27w + 2*10w. configuration and status diagnosis is done via spi. additionally, there is a current sense signal available for each channel that is routed via a multiplexer to a single diagnosis pin. the spoc - BTS5566G provides a fail-safe function via limp home input pin. product summary operating voltage power switch v bb 4.5 ? 28 v logic supply voltage v dd 3.8 ? 5.5 v over voltage protection v bb(az,min) 40 v maximum stand-by current at 25 c i bb(off) 3 a on-state resistance at t j = 150 channel 0, 1 channel 2 channel 3,4 r ds(on) max 49 m ? 64 m ? 180 m ? spi access frequency f sclk(max) 2mhz
spi power controller spoc - BTS5566G overview data sheet 4 rev. 1.3, 2007-10-30 basic features ? 8 bit serial peripheral interface (daisy chain capable spi) for control and diagnostics ? cmos compatible paralle l input pins for each channel provide straightforward pwm operation ? selectable and- / or-combination for parallel inputs (pwm control) ? very low stand-by current ? optimized electromagnetic compatibility (emc) for bulbs ? stable behavior at under voltage ? device ground independent from load ground ? green product (rohs-compliant) ? aec qualified protective functions ? reverse battery protecti on with external components ? short circuit protection ? over load protection ? multi step current limitation ? thermal shutdown with latch ? over voltage protection ? loss of ground protection ? electrostatic discha rge protection (esd) diagnostic functions ? multiplexed proportional load current sense signals (is) ? enable function for current s ense signal configurable via spi ? high accuracy of current sense signal at wide load current range ? feedback on over temperature and over load via spi ? multiplexed switch bypass monitor provides short circuit to v bb detection application specific functions ? fail-safe activation via lhi pin and configuration via input pins applications ? high-side power switch for 12 v grounded loads in automotive application ? especially designed for standard exterior lighting like tail light, brake light, reverse light, parking light, license plate lighting and turn signal indicators ? replaces electromechanical relays, fuses and discrete circuits
data sheet 5 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G overview figure 1 application example abbreviations: bl brake light (21 w, 27 w) rl reverse light (21 w, 27 w) tl tail light (5 w, 7 w, 10 w) lic license plate lighting (5 w, 10 w) ind indicator / flasher (21 w, 27 w) applicat ion rear . emf ind tl rl bl ind tl rl bl spoc lic limp home control fail safe system limp home control watchdog spoc - BTS5566G spoc - BTS5566G 180 m ? 49 m ? 49 m ? 64 m ? 180 m ? 180 m ? 64 m ? 49 m ? 49 m ? 180 m ?
spi power controller spoc - BTS5566G block diagram data sheet 6 rev. 1.3, 2007-10-30 2 block diagram the spoc - BTS5566G is a five channel high-side powe r switch in pg-dso-36-34 package providing embedded protective functions. an 8 bit serial peripheral interface (spi) is used for configuration and diagnosis. the spi can be used in daisy chain configuration. the device provides a current sense signal per channel th at is multiplexed to the diagnosis pin is. it can be enabled and disabled via spi commands. an over load and over temperature flag is provided in the spi diagnosis word. a multiplexed switch bypass monitor provides diagnosis at short-circuit to v bb . the power transistors are built by n-channel vert ical power mosfets with c harge pumps. the device is monolithically integr ated in smart si pmos technology. figure 2 block diagram spoc - BTS5566G 4 3 2 1 channel 0 power supply driver logic gate contr ol & charge pump clamp for inductive load load cur rent limitation load current sense tem perature sensor esd protection in2 in3 in4 in0 in1 gnd spi curr ent sense m ultiplexer is so sclk si cs lhi limp home contr ol switch bypass m onitor pwm contr ol vbb out3 out2 out1 out0 out4
data sheet 7 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G block diagram 2.1 terms the following figure shows all term s used in this data sheet. figure 3 terms in all tables of electrical characteri stics is valid: channel related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds4 ). all spi register bits are marked as follows: addr.parameter (e.g. hwcr.ctl ). in spi register description, the values in bold letters (e.g. 0 ) are default values. i in 0 v in 0 i in 1 v in 1 v so i in 2 v si i in 3 v bb v cs i is i bb in0 in1 in2 in3 is vbb i cs cs sclk v in 2 v in 3 v in 4 v dd i dd i so vdd so i in 4 in4 v is i lhi lhi i si si v lhi out0 i l0 out1 out3 out4 i l1 i l3 i l4 out2 i l2 gnd i gnd i sc lk v sc l k v out1 v ds1 v out4 v ds4 v out3 v out2 v out0 v ds3 v ds2 v ds0
spi power controller spoc - BTS5566G pin configuration data sheet 8 rev. 1.3, 2007-10-30 3 pin configuration 3.1 pin assignment spoc - BTS5566G figure 4 pin configuration pg-dso-36-34 (top view) out1 out1 out1 vbb 36 35 34 33 32 31 vbb 1 2 3 4 5 6 7 8 30 29 out0 out0 out0 out0 out3 out3 out4 out1 28 27 26 25 24 23 9 10 11 12 13 14 15 16 22 21 out2 out2 out2 out2 out4 vbb 18 19 vbb 20 17 cs sclk si so vdd gnd lhi n.c. is in1 in0 in2 in3 in4 n.c. vbb
data sheet 9 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G pin configuration 3.2 pin definitions and functions pin symbol i/o function power supply pins 1, 16, 18, 19, 36 1) 1) all vbb pins have to be connected. vbb ? positive power supply for high-s ide power switch and limp home block 3 vdd ? logic supply (5 v) 2 gnd ? ground connection parallel input pins 8 in0 i input signal of channel 0 9 in1 i input signal of channel 1 10 in2 i input signal of channel 2 11 in3 i input signal of channel 3 12 in4 i input signal of channel 4 power output pins 32, 33, 34, 35 2) 2) all output pins of each channel have to be connected. out0 o protected high-side power output of channel 0 28, 29,30, 31 2) out1 o protected high-side power output of channel 1 24, 25,26, 27 2) out2 o protected high-side power output of channel 2 22, 23 2) out3 o protected high-side power output of channel 3 20, 21 2) out4 o protected high-side power output of channel 4 spi & diagnosis pins 7 cs i chip select of spi interface (low active) 6 sclk i serial clock of spi interface 5 si i serial input of spi interface 4 so o serial output of spi interface 13 is o diagnosis output signal limp home pins 14 lhi i limp home mode activation other pins 15, 17 n.c. ? not connected, floating
spi power controller spoc - BTS5566G electrical characteristics data sheet 10 rev. 1.3, 2007-10-30 4 electrical characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 c to +150 c; all volt ages with respect to ground, positive current flowing into pin. (unless otherwise specified). pos. parameter symbol limit values unit conditions min. max. supply voltage 4.1.1 power supply voltage v bb -0.3 28 v ? 4.1.2 logic supply voltage v dd -0.3 5.5 v ? 4.1.3 reverse polarity voltage according figure 23 - v bat(rev) ?16v t jstart = 25 c t 2min 2) 4.1.4 supply voltage for full sh ort circuit protection (single pulse) ( t j(0) = -40 c ? 150 c) v bb(sc) 020v r ecu = 20m ? r cable = 16m ? /m l cable = 1h/m l = 0 or 5m 3) 4.1.5 voltage at power transistor v ds ?54v? 4.1.6 supply voltage for load dump protection v bb(ld) ?41v r i = 2 ? 4) t = 400ms 4.1.7 current through ground pin i gnd -100 25 ma t 2min 4.1.8 current through vdd pin i dd -25 12 ma t 2min power stages 4.1.9 load current i l -i l(lim) i l(lim) a 5) diagnosis pin 4.1.10 current through sense pin is i is -10 10 ma t 2min input pins 4.1.11 voltage at input pins v in -0.3 8.0 v ? 4.1.12 current through input pins i in -0.75 -2.0 0.75 2.0 ma ? t 2min spi pins 4.1.13 voltage at chip select pin v cs -0.3 5.7 v ? 4.1.14 current through chip select pin i cs -2.0 2.0 ma t 2min 4.1.15 voltage at serial input pin v si -0.3 5.7 v ? 4.1.16 current through serial input pin i si -2.0 2.0 ma t 2min 4.1.17 voltage at serial clock pin v sclk -0.3 5.7 v ? 4.1.18 current through serial clock pin i sclk -2.0 2.0 ma t 2min 4.1.19 current through serial output pin so i so -2.0 2.0 ma t 2min limp home pins 4.1.20 voltage at limp home input pin v lhi -0.3 8.0 v ? 4.1.21 current through limp home input pin i lhi -0.75 -2.0 0.75 2.0 ma ? t 2min
data sheet 11 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G electrical characteristics note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. temperatures 4.1.22 junction temperature t j -40 150 c? 4.1.23 dynamic temperature increase while switching ? t j ?60k? 4.1.24 storage temperature t stg -55 150 c? esd susceptibility 4.1.25 esd resistivity hbm out pins other pins v esd -4 -2 4 2 kv hbm 6) ? ? 1) not subject to production test, specified by design. 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm bo ard with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). 3) in accordance to aec q100-012 and aec q101-006. 4) r i is the internal resistance of the load dump pulse generator. 5) current limitation is a protec tion feature. operation in curre nt limitation is considered as ?outside? normal operating range . protection features are not designed for continuous repetitive operation. 6) esd resistivity, hbm according to eia/jesd 22-a 114b (1.5k ? , 100pf). absolute maximum ratings 1) t j = -40 c to +150 c; all volt ages with respect to ground, positive current flowing into pin. (unless otherwise specified). pos. parameter symbol limit values unit conditions min. max.
spi power controller spoc - BTS5566G power supply data sheet 12 rev. 1.3, 2007-10-30 5 power supply the spoc - BTS5566G is supplied by two supply voltages v bb and v dd . the v bb supply line is used by the power switches. the v dd supply line is used by the spi related circuitr y and for driving the so line. a capacitor between pins vdd and gnd is recommended. there is a power-on reset function implemented for the v dd logic supply voltage. after start-up of the logic power supply, all spi registers are reset to their default values. the spi interface including da isy chain function is active as soon as v dd is provided in the spec ified range independent of v bb . 5.1 power supply modes the following table shows all possible power supply modes for v bb , v dd and the pin lhi. to achieve stand-by mode, the limp home block must be disa bled (lhi = 0 v), all channels must be switched off and the thermal latches have to be cleared. as a result the stand-by current i bb(off) is valid as listed. in case of active v dd supply, the idle mode parameters are valid only, when additionally all spi registers are at default values (see section 9.6 ) e.g. after a reset command. power supply modes vbb 0v 0v 0v 0v 13.5v 13.5v 13.5v 13.5v vdd 0v0v5v5v0v0v5v5v lhi 0v5v0v5v0v5v0v5v profet operating ???? ???? limp home mode ????? ? ? ? spi (logic) reset reset ?? reset reset ? reset stand-by current ???? ? ??? idle current ?????? ? 1) 1) when all channels are in off-state and al l spi registers are at default values. ? diagnosis ?????? ?? 2) 2) current sense diagnosis not available in limp home mode.
data sheet 13 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G power supply 5.2 reset there are several reset trigger implemented in the device. they reset the spi registers to their default values. the power stages as well as the analog watchdog bl ock are not affected by the reset signals. the first spi transmission after any kind of reset co ntains at pin so the read information from register out , and the transmission error bit ter is set. power-on reset the power-on reset is released, when v dd voltage level is higher than v dd(po) . the spi interface can be accessed after wake up time t wu(po) . reset command there is a reset command available to reset all register bi ts of the register bank an d the diagnosis registers. as soon as hwcr.rst = 1, a reset is triggered equivalent to power-on reset. the spi interface can be accessed after transfer delay time t cs(td) . limp home mode in limp home mode, the spi write-registers are reset. t he spi interface is operating normally, so the limp home register bit lhi as well as the error flags can be read.
spi power controller spoc - BTS5566G power supply data sheet 14 rev. 1.3, 2007-10-30 5.3 electrical characteristics note: characteristics show the deviation of parameter at the given supply voltage and junction temperature. typical values show the typical parameter s expected from manufacturing at v bb = 13.5 v, v dd = 4.3 v and t j = 25 c. electrical characteristics power supply unless otherwise specified: v bb = 9 v to 16 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c. typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c. pos. parameter symbol limit values unit test conditions min. typ. max. 5.3.1 operating voltage v bb 4.5 ? 28 v ? 5.3.2 stand-by current for whole device with loads i bb(off) ? ? ? 1.2 ? ? 3 3 50 a v dd = 0 v v lhi = 0 v v in = 0 v t j = 25 c t j 85 c 1) t j = 150 c 1) not subject to production test, specified by design. idle current for whol e device with loads i bb(idle) ? ? ? ? ? ? 3 3 50 a v dd = 5 v v lhi = 0 v v in = 0 v t j = 25 c t j 85 c 1) t j = 150 c 5.3.3 logic supply voltage v dd 3.8 ? 5.5 v ? 5.3.4 logic supply current i dd ? 45 150 a v cs = 0 v f sclk = 0 hz 5.3.5 logic idle current i dd(idle) ?1535 a v cs = v dd f sclk = 0 hz 5.3.6 operating current for whole device i gnd ?1020ma f sclk = 0 hz 5.3.7 power-on reset threshold voltage v dd(po) ??3.8v? 5.3.8 power-on wake up time t wu(po) ? ? 500 s?
data sheet 15 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G power supply 5.4 command description hwcr hardware configuration register w/r 43210 read rst 0 sbm pwm ctl write rst 0 0 pwm ctl field bits type description rst 4 r reset command 0 normal operation 1 device in reset due to limp home mode rst 4 w reset command 0 normal operation 1 execute reset command
spi power controller spoc - BTS5566G power stages data sheet 16 rev. 1.3, 2007-10-30 6 power stages the high-side power stages are built by n-channel vert ical power mosfets (dmos) with charge pumps. there are five channels implemented in the device. each channel can be switched on via an input pin or via spi register out . 6.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage v bb as well as on the junction temperature t j . figure 5 shows those dependencies. the behavior in reverse polarity mode is described in section 7.3 . figure 5 typical on-state resistance 6.2 input circuit there are two ways of using the input pins in combin ation with the out spi regi ster by programming the hwcr.pwm parameter. ? hwcr.pwm = 0: a channel is switched on either by the according out register bit or the input pin. ? hwcr.pwm = 1: a channel is switched on by the according out register bit only, when the input pin is high. in this configuration, a pwm signal can be given to the input pin and the channel is activated by the spi register out. figure 6 shows the complete input switch matrix. figure 6 input switch matrix the current sink to ground at the input pins ensures that the input signal is low in ca se of an open input pin. the zener diode protects the inpu t circuit against esd pulses. 50 100 150 200 250 0 5 10 15 20 25 r ds(on) /m ? v bb /v channel 0, 1 (bulb) channel 2 (bulb) channel 3, 4 0 50 100 150 200 250 -50 -25 0 25 50 75 100 125 150 r ds(on) /m ? t / c channel 0, 1 (bulb) channel 2 (bulb) channel 3, 4 v bb = 13.5 v t j = 25 c inputmatrix.emf in0 in1 in2 in3 in4 gate driver 2 gate driver 1 gate driver 0 gate driver 4 gate driver 3 & or out2 out1 out0 out4 out3 & or & or & or & or pwm i in0 i in1 i in2 i in3 i in4
data sheet 17 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G power stages 6.3 power stage output the power stages are built to be us ed in high side configuration ( figure 7 ). figure 7 power stage output the power dmos switches with a dedicated slope, which is optimized in terms of emc emission. figure 8 switching a load (resistive) when switching off inductive loads wi th high-side switches, the voltage v out drops below ground potential, because the inductance intends to continue driving the cu rrent. to prevent destruction of the device, there is a voltage clamp mechanism implemented that limits th at negative output voltage to a certain level ( v on(cl) ( 6.4.3 )). see figure 7 for details. the maximum allowe d load inductance is limited. output.emf out gnd v out vbb v on v bb in v out t switchon.emf t on t off t 90% 10% 70% d v / d t on 30% 70% d v / d t off 30%
spi power controller spoc - BTS5566G power stages data sheet 18 rev. 1.3, 2007-10-30 6.4 electrical characteristics electrical characteristic power stages unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c. typical values: v bb = 13.5 v, t j = 25 c. pos. parameter symbol limit values unit test conditions min. typ. max. output characteristics 6.4.1 on-state resistance r ds(on) m ? channel 0, 1 ? ? 22.3 38 ? 49 1) t j = 25 , i l =2.6a t j = 150 , i l =2.6a channel 2 ? ? 25.2 49 ? 64 1) t j = 25 c , i l =2.6a t j = 150 c , i l =2.6a channel 3, 4 ? ? 72.9 141 ? 180 1) t j = 25 c , i l =1a t j = 150 c , i l =1a 6.4.2 output voltage drop limitation at small load currents v ds(nl) mv channel 0, 1, 2 ? 35 ? i l = 35 ma channel 3, 4 ? 35 ? i l = 35 ma 6.4.3 output clamp v on(cl) 40 47 54 v i l = 20 ma 6.4.4 output leakage current per channel i l(off) a v in = 0 v out.outn = 0 channel 0, 1 ? ? 0.1 ? 10 40 stand-by not stand-by channel 2 ? ? 0.1 ? 10 40 stand-by not stand-by channel 3, 4 ? ? 0.1 ? 8 40 stand-by not stand-by 6.4.5 inverse current capability per channel - i l(ic) a no influence on functionality of unaffected channels 1) channel 0, 1, 2 ? 2.5 ? ? channel 3, 4 ? 1.0 ? ? thermal resistance 6.4.6 junction to case r thjc ??20 k/w 1) 6.4.7 junction to ambient, all channels active r thja ?40?k/w 1) 2) input characteristics 6.4.8 l-input level v in(l) -0.3 ? 1.0 v ? 6.4.9 h-input level v in(h) 2.6?5.5v? 6.4.10 l-input current i in(l) 32575 a v in = 0.4 v 6.4.11 h-input current i in(h) 10 40 75 a v in = 5 v
data sheet 19 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G power stages timings 6.4.12 turn-on time to 90% v bb t on s v bb = 13.5 v channel 0, 1, 2 ? ? 250 r l = 6.8 ? channel 3, 4 ? ? 250 r l = 18 ? 6.4.13 turn-off time to 10% v bb t off s v bb = 13.5 v channel 0, 1, 2 ? ? 290 r l = 6.8 ? channel 3, 4 ? ? 290 r l = 18 ? 6.4.14 turn-on slew rate 30% to 70% v bb d v / d t on v/ s v bb = 13.5 v channel 0, 1, 2 0.1 ? 0.5 r l = 6.8 ? channel 3, 4 0.1 ? 0.5 r l = 18 ? 6.4.15 turn-off slew rate 70% to 30% v bb -d v / d t off v/ s v bb = 13.5 v channel 0, 1, 2 0.1 ? 0.5 r l = 6.8 ? channel 3, 4 0.1 ? 0.5 r l = 18 ? 1) not subject to production test, specified by design. 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). electrical characteristic power stages unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c. typical values: v bb = 13.5 v, t j = 25 c. pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - BTS5566G power stages data sheet 20 rev. 1.3, 2007-10-30 6.5 command description out output configuration registers w/r rb543210 read/write 0 0 out4 out3 out2 out1 out0 field bits type description outn n = 4 to 0 nr/w set output mode for channel n 0 channel n is switched off 1 channel n is switched on hwcr hardware configuration register w/r 43210 read rst 0 sbm pwm ctl write rst 0 0pwm ctl field bits type description pwm 1 rw pwm configuration 0 input signal or-combined with according out register bit 1 input signal and-comb ined with according out register bit
data sheet 21 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G protection functions 7 protection functions the device provides embedded protective functions, wh ich are designed to prevent ic destruction under fault conditions described in this data sheet. fault condit ions are considered as ?out side? normal operating range. protective functions are neither designed fo r continuous nor for repetitive operation. 7.1 over load protection the load current i l is limited by the device itself in case of over load or short circuit to ground. there are multiple steps of current limitation which are select ed automatically depending on the voltage v ds across the power dmos. please note that the voltage at the out pin is v bb - v ds . please refer to following figures for details. figure 9 current limitation channels 0, 1 (minimum values) figure 10 current limitation channels 2 (minimum values) figure 11 current limitation channels 3, 4 (minimum values) current limitation to the value i l(lim) is realized by increasing the resistance of the output channel, which leads to rapid temperature rise inside. currentlimitation01 .emf 5 101520 v ds 25 i l 5 10 15 20 25 currentlimitation2 .emf 5 101520 v ds 25 i l 5 10 15 20 25 currentlimitation34 .emf i l 5 101520 v ds 25 2 4 6 8 10 12
spi power controller spoc - BTS5566G protection functions data sheet 22 rev. 1.3, 2007-10-30 7.2 over temperature protection a temperature sensor for each channel causes an overheat ed channel to switch off la tched to prevent destruction ( also even in case of v dd = 0v). all over temperature latches are cleared by spi command hwcr.ctl = 1. figure 12 shut down by over temperature 7.3 reverse polarity protection in reverse polarity mode, power dissipation is caused by the intrinsic body diode of each dmos channel as well as each esd diode of the logic pins. the reverse current through the channels has to be limited by the connected loads. the current trough the ground pin, sense pin is, the logic power supply pin vdd, the spi pins and the watchdog pins has to be limited as well (please refer to the maximum ratings listed on page 10 ). note: no other protection mechanism such as temperature pr otection or current limitation is active during reverse polarity. 7.4 over voltage protection in addition to the output clamp for inductive loads as described in section 6.3 , there is a clamp mechanism available for over voltage protection. the current throug h the ground connection has to be limited during over voltage. please note that in case of over voltage the pin gnd may have a hi gh voltage offset to the module ground. 7.5 loss of ground in case of complete loss of the device ground connections, but connected load ground, the spoc - BTS5566G securely changes to or stays in off-state. 7.6 loss of v bb in case of loss of v bb connection in on-state, all inductance of the loads has to be demagnetized through the ground connection or through an additional path from vbb to ground. when a diode is used in the ground path for reverse polarity reasons, the ground co nnection is not available for demagnetiz ation. then for ex ample, a resistor can be placed in parallel to t he diode or a suppressor diode ca n be used between vbb and gnd. in i l i is t i l(lim) t t err t overload.emf ctl = 1
data sheet 23 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G protection functions 7.7 electrical characteristics electrical characteri stics protection functions unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. over load protection 7.7.1 load current limitation i l(lim) a v ds = 7 v channel 0 24 ? 48 1) ? channel 1 24 ? 48 1) ? channel 2 24 ? 48 1) ? channel 3 12 ? 27 1) ? channel 4 12 ? 27 1) ? 7.7.2 initial short ci rcuit shut down time t off(sc) s t jstart = 25 c 1) 1) not subject to production test, specified by design. channel 0, 1 ? 550 ? ? channel 2 ? 400 ? ? channel 3, 4 ? 400 ? ? over temperature protection 7.7.3 thermal shut down temperature t j(sc) 150 170 1) ? c? 7.7.4 thermal hysteresis ? t j ?7?k 1) reverse battery 7.7.5 drain-source diode voltage ( v out > v bb ) - v ds(rev) mv t j = 150 c channel 0, 1 ? 600 ? i l = -2.5 a channel 2 ? 620 ? i l = -2.5 a channel 3, 4 ? 600 ? i l = -1 a over voltage 7.7.6 overvoltage protection v bb(az) 40 47 54 v i bb = 4 ma loss of gnd protection 7.7.7 output current while gnd disconnected i l(gnd) ??1ma 1)
spi power controller spoc - BTS5566G protection functions data sheet 24 rev. 1.3, 2007-10-30 7.8 command description hwcr hardware configuration register w/r 43210 read rst 0 sbm pwm ctl write rst 0 0 pwm ctl field bits type description ctl 0 rw clear thermal latch 0 thermal latches are untouched 1 command: clear a ll thermal latches
data sheet 25 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G diagnosis 8 diagnosis for diagnosis purpose, the spoc - BTS5566G provides a current sense signal and the diagnosis word at spi. there is a current sense multiplexer implemented that is controlled via spi. the sense si gnal can also be disabled by spi command. a switch bypass monito r allows to detect a short circuit be tween the output pin and the battery voltage. please refer to figure 13 for details. figure 13 block diagram: diagnosis for diagnosis feedback at different oper ation modes, please see following table. table 1 operation modes 1) 1) l = low level, h = high level, z = high impedance, potential depends on leakage currents and external circuit x = undefined operation mode input level out.outn output level v out current sense i is error flag errn 2) 2) the error flags are latched until they are tr ansmitted in the standard diagnosis word via spi hwcr. sbm normal operation (off) l / 0 (off-state) gnd z 0 1 short circuit to gnd gnd z 0 1 over temperature z z 0 x short circuit to v bb v bb z00 open load z z 0 x normal operation (on) h / 1 (on-state) ~ v bb i l / k ilis 00 current limitation < v bb z1x short circuit to gnd ~gnd z 1 1 over temperature z z 1 3) 3) the over temperature flag is set latc hed and can be cleared by spi command hwcr.ctl x short circuit to v bb v bb < i l / k ilis 00 open load v bb z00 channel 0 load curr ent sense diagnosis.emf r is current sense multiplexer is t gate contr ol load curr ent limitation latch tem per atur e sensor err0 or latch dcr.mux sbm hwcr. out4 out3 out2 out1 out0 vbb v bb v ds(sb) i is 0
spi power controller spoc - BTS5566G diagnosis data sheet 26 rev. 1.3, 2007-10-30 8.1 diagnosis word at spi the standard diagnosis at the spi in terface provides information about each channel. the error flags, an or combination of the over temperature flags and the over lo ad monitoring signals are provided in the spi standard diagnosis bits errn . the over load monitoring signals are latched in the erro r flags and cleared each time the standard diagnosis is transmitted via spi. in detail, they are cleared between the second and third raising edge of the sclk signal. the over temperature flags, which cause an overheated channel to stay switched off, ar e latched directly at the gate control block. the latches are cleared by spi command hwcr.ctl . please note: the over temperature information is latched twice. when transmitting a clear thermal latch command ( hwcr.clt ), the error flag is cleared during command transmission of th e next spi frame and ready for latching after the third raising edge of the sclk signal. as a result, th e first standard diagnosis information after a ctl command will indicate a failure mode at the previously affected channels although the thermal latches have been cleared already. in case of continuous over load, the error flags are set again immediately because of the over load monitoring signal. in case of high duty cyle (off state of output < t off-state_min ) the v ds might not be equal to v dd during the off state of the power mosfet. the over load moni toring signals might be set and latched in the error flags. see application note ?software strategy for diagnosis during pwm-operation? for more details. 8.2 load current sense diagnosis there is a current sense signal available at pin is which provides a current proportional to the load current of one selected channel. the selection is done by a multiplexer which is configured via spi. the current sense signal (ratio k ilis = i l / i s ) is provided as long as no failure mode occurs. usually a resistor r is is connected from the current sense pin to gn d. it is recommended to use resistors 2.5 k ?< r is <7k ? . a typical value is 3.3 k ? . figure 14 current sense ratio k ilis channel 0,1 1) 1) the curves show the behavior based on characterization dat a. the marked points are guaranteed in this data sheet in section 8.4 (position 8.4.1 ). 1000 2000 3000 4000 5000 6000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 k ilis i l0,1 /a dummy t j = 150 c dummy t j = -40 c
data sheet 27 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G diagnosis figure 15 current sense ratio k ilis channel 2 1) figure 16 current sense ratio k ilis channel 3, 4 1) in case of over current as well as over temperature, th e current sense signal of the affected channel is switched off. to distinguish between over temperature and over load, the spi diagnosis word can be used. whereas the over load flag is cleared every time the diagnosis is trans mitted, the over temperature flag is cleared by a dedicated spi command ( hwcr.ctl ). details about timings between the current sense signal i is and the output voltage v out and the load current i l can be found in figure 17 . 1) the curves show the behavior based on characterization dat a. the marked points are guaranteed in this data sheet in section 8.4 (position 8.4.1 ). 1000 2000 3000 4000 5000 6000 0 0.5 1 1.5 2 2.5 3 3.5 4 k ilis i l2 /a dummy bulb: t j = 150 c dummy bulb: t j = -40 c 500 1000 1500 2000 2500 3000 0 0.5 1 1.5 2 k ilis i l3,4 /a dummy t j = 150 c dummy t j = -40 c
spi power controller spoc - BTS5566G diagnosis data sheet 28 rev. 1.3, 2007-10-30 figure 17 timing of current sense signal current sense multiplexer there is a current sense multiplexer implemented in the spoc - BTS5566G that routes the sense current of the selected channel to the diagnosis pin is. the channel is selected via spi register dcr.mux . the sense current also can be disabled by spi register dcr.mux . for details on timing of the current sense multiplexer, please refer to figure 18 . figure 18 timing of current sense multiplexer 8.3 switch bypass diagnosis to detect short circuit to v dd , there is a switch bypass monitor implemente d. in case of short circuit between the output pin out and v bb in on-state, the current will fl ow through the power transistor as well as through the short circuit (bypass) with undefined ratio. as a result, the current sense signal will show lower values than expected by the load current. in o ff-state, the outp ut voltage will stay close to v bb potential which means a small v ds . the switch bypass monitor compares the voltage v ds across the power transistor of that channel which is selected by the current sense multiplexer ( dcr.mux ) with threshold v ds(sb) . the result of comparison can be read in spi register hwcr.sbm . the switch bypass monitor is active in on- as well as in off-state. sensetiming.emf in v out i is t t t i l t on t on t sis(on) t sis(lc) off t off t dis(off) off m u xtim in g.e m f cs i is t t 000 dcr.mux 001 111 111 t sis(en) t sis(mux) t dis(mux)
data sheet 29 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G diagnosis 8.4 electrical characteristics electrical characteristics diagnosis unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. load current sense 8.4.1 current sense ratio k ilis channel 0, 1: i l = 1.3 a i l = 2.6 a i l = 6.0 a 2400 2400 2500 3100 3000 3000 3800 3500 3500 t j = -40 c ? ? i l = 1.3 a i l = 2.6 a i l = 6.0 a 2450 2450 2700 3030 3000 3000 3600 3350 3300 t j = 150 c ? ? channel 2: i l = 1.3 a i l = 2.6 a i l = 3.5 a 2400 2400 2500 3100 3000 3000 3800 3500 3500 t j = -40 c ? ? i l = 1.3 a i l = 2.6 a i l = 3.5 a 2450 2450 2700 3000 3000 3000 3600 3350 3300 t j = 150 c ? ? channel 3, 4: i l = 0.3 a i l = 0.6 a i l = 1.3 a i l = 2.0 a 1220 1250 1280 1310 1625 1565 1520 1520 2030 1880 1760 1730 t j = -40 c ? ? ? i l = 0.3 a i l = 0.6 a i l = 1.3 a i l = 2.0 a 1270 1340 1360 1360 1520 1520 1520 1520 1770 1700 1680 1680 t j = 150 c ? ? ? 8.4.2 current sense voltage limitation v is(lim) -8% v dd 8% v i is = 1 ma 8.4.3 current sense leakage / offset current i is(en) ??2 a i l = 0 dcr.mux = 000 b 8.4.4 current sense leakage, while diagnosis disabled i is(dis) ??1 a i l = i l(nom) dcr.mux = 111 b 8.4.5 current sense settling time after channel activation t sis(on) ??300 s v bb = 13.5 v i l = i l(nom) r is = 4.7 k ? 8.4.6 current sense desettling time after channel deactivation t dis(off) ??25 s v bb = 13.5 v 1) i l = i l(nom) r is = 4.7 k ?
spi power controller spoc - BTS5566G diagnosis data sheet 30 rev. 1.3, 2007-10-30 8.4.7 current sense settling time after change of load current channel 0, 1, 2 channel 3, 4 t sis(lc) ? ? ? ? 30 30 s v bb = 13.5 v 1) r is = 4.7 k ? i l = 1.3 a to 2.6 a i l = 0.6 a to 1.3 a 8.4.8 current sense settling time after current sense activation t sis(en) ??25 s r is = 4.7 k ? dcr.mux :111 b -> 000 b 8.4.9 current sense settling time after multiplexer channel change t sis(mux) ??30 s r is = 4.7 k ? dcr.mux :000 b -> 001 b 8.4.10 current sense deactivation time t dis(mux) ??25 s 1) r is = 4.7 k ? dcr.mux : 001 b -> 111 b 8.4.11 off state time during pwm operation t off state_min 350 ? ? s ? switch bypass monitor 8.4.12 switch bypass monitor threshold v ds(sb) 0.7 ? 2.5 v ? 1) not subject to production test, specified by design. electrical characteristics diagnosis unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 31 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G diagnosis 8.5 command description dcr diagnosis control registers 43210 0 0mux field bits type description mux 2:0 rw set current sense multiplexer configuration 000 current sense of channel 0 is routed to is pin 001 current sense of channel 1 is routed to is pin 010 current sense of channel 2 is routed to is pin 011 current sense of channel 3 is routed to is pin 100 current sense of channel 4 is routed to is pin 101 is pin is high impedance 110 is pin is high impedance 111 is pin is high impedance hwcr hardware configuration register w/r 43210 read rst 0 sbm pwm ctl write rst 0 0 pwm ctl field bits type description sbm 2 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) 1) invalid in stand-by mode standard diagnosis cs76543210 ter 0 lhi 0 err4 err3 err2 err1 err0 field bits type description errn n = 4 to 0 nr error flag channel n 0 normal operation 1 failure mode occurred
spi power controller spoc - BTS5566G serial peripheral interface (spi) data sheet 32 rev. 1.3, 2007-10-30 9 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex sync hronous serial slave interface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the rate given by sclk. the falling edge of cs indicates the beginning of an access. da ta is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferr ed. the interface provides daisy chain capability. figure 19 serial peripheral interface 9.1 spi signal description cs - chip select: the system micro controller selects the spoc - BTS5566G by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the requested information is transferred into the shift register. ? so changes from high impedance state to high or lo w state depending on the logi c or combination between the transmission error flag ( ter ) and the signal level at pin si. as a re sult, even in daisy chain configuration, a high signal indicates a faulty transmission. this inform ation stays available to the first rising edge of sclk. cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faul ty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. sclk - serial clock: this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shifte d-in at this pin, the most si gnificant bit first. si informat ion is read on the falling edge of sclk. the input data consists of two parts, co ntrol bits followed by dat a bits. please refer to section 9.5 for further information. so serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appe ar at the so pin following the risi ng edge of sclk. please refer to section 9.5 for further information. lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 cs msb msb so si cs sclk time spi.emf
data sheet 33 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G serial peripheral interface (spi) 9.2 daisy chain capability the spi of spoc - BTS5566G provides daisy chain capabili ty. in this configuration several devices are activated by the same cs signal mcs . the si line of one device is connecte d with the so line of another device (see figure 20 ), in order to build a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the ma ster device provides the master cl ock mclk which is connected to the sclk line of each device in the chain. figure 20 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out occures at the so pin. after eight sclk c ycles, the data transfer for one device has been finished. in single chip configuration, the cs line must turn high to make the devic e accept the transferred data. in daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. when using three devices in daisy chain, three times eight bits have to be shifted through the devices. after that, the mcs line must turn high (see figure 21 ). figure 21 data transfer in daisy chain configuration 9.3 timing diagrams figure 22 timing diagram spi access si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _dasychain. emf mi mo mcs mclk si device 3 si device 2 si device 1 so device 3 so device 2 so device 1 time spi _dasychain2. emf cs sclk si t cs(lead) t cs( td ) t cs( la g ) t scl k( h) t scl k( l ) t sclk( p) t si( su ) t si( h ) so t so( v) t so(en) t so( d is) 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd 0.7 v dd 0.2 v dd spi timing. emf
spi power controller spoc - BTS5566G serial peripheral interface (spi) data sheet 34 rev. 1.3, 2007-10-30 9.4 electrical characteristics electrical characteristics spi unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v dd = 3.8 v to 5.5 v typical values: v bb = 13.5 v, t j = 25 c, v dd = 4.3 v pos. parameter symbol limit values unit test conditions min. typ. max. input characteristics (cs , sclk, si) 9.4.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) -0.3 -0.3 -0.3 ? ? ? 1.0 1.0 1.0 v v dd = 4.3 v ? ? ? 9.4.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 2.6 2.6 2.6 ? ? ? 5.5 5.5 5.5 v v dd = 4.3 v ? ? ? 9.4.3 l-input pull-up current at cs pin i cs(l) 10 30 85 a v dd = 4.3 v, v cs = 0 v 9.4.4 h-input pull-up current at cs pin i cs(h) 3?85 a v dd = 4.3 v, v cs = 2.6 v 9.4.5 l-input pull-down current at pin sclk si i sclk(l) i si(l) 3 3 ? ? 75 75 a v dd = 4.3 v v sclk = 0.4 v v si = 0.4 v 9.4.6 h-input pull-down current at pin sclk si i sclk(h) i si(h) 10 10 30 30 75 75 a v dd = 4.3 v v sclk = 4.3 v v si = 4.3 v output characteristics (so) 9.4.7 l level output voltage v so(l) 0?0.5v i so = -0.5 ma 9.4.8 h level output voltage v so(h) v dd - 0.5 v ? v dd v i so = 0.5 ma, v dd = 4.3 v 9.4.9 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 9.4.10 serial clock freqency f sclk 0?2mhz? 9.4.11 serial clock period t sclk(p) 500 ? ? ns ? 9.4.12 serial clock high time t sclk(h) 250 ? ? ns ? 9.4.13 serial clock low time t sclk(l) 250 ? ? ns ? 9.4.14 enable lead time (falling cs to rising sclk) t cs(lead) 1?? s? 9.4.15 enable lag time (falling sclk to rising cs ) t cs(lag) 1?? s? 9.4.16 transfer delay time (rising cs to falling cs ) t cs(td) 1?? s? 9.4.17 data setup time (required time si to falling sclk) t si(su) 100 ? ? ns ? 9.4.18 data hold time (falling sclk to si) t si(h) 100 ? ? ns ? 9.4.19 output enabl e time (falling cs to so valid) t so(en) ??1 s c l = 20 pf 1)
data sheet 35 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G serial peripheral interface (spi) 9.4.20 output disabl e time (rising cs to so tri-state) t so(dis) ??1 s c l = 20 pf 1) 9.4.21 output data valid time with capacitive load t so(v) ??250ns c l = 20 pf 1) 1) not subject to production test, specified by design. electrical characteristics spi unless otherwise specified: v bb = 9 v to 16 v, t j = -40 c to +150 c, v dd = 3.8 v to 5.5 v typical values: v bb = 13.5 v, t j = 25 c, v dd = 4.3 v pos. parameter symbol limit values unit test conditions min. typ. max.
spi power controller spoc - BTS5566G serial peripheral interface (spi) data sheet 36 rev. 1.3, 2007-10-30 9.5 spi protocol note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame the output at spi signal so will cont ain the requested information. a ne w command can be executed in the second frame. cs 1) 1) the so pin shows this information between cs hi -> lo and first sclk lo -> hi transition. 76543210 write register si 1 addr data read register si 0 addr xxxx0 read standard diagnosis si 0xxxxxx1 standard diagnosis so ter 0 lhi x err4 err3 err2 err1 err0 second frame of read command so ter 1 addr data field bits type description ter cs r transmission error 0 previous transmission was succe ssful (modulo 8 clocks received) 1 previous transmission failed or first transmi ssion after reset addr 6:5 rw address pointer to register for read and write command data 4:0 rw data data written to or read from register selected by address addr lhi 6 r limp home input pin 0 l-input signal at pin lhi 1 h-input signal at pin lhi errx x = 4 to 0 xr diagnosis of channel x 0 no failure 1 over temperature, over load or short circuit
data sheet 37 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G serial peripheral interface (spi) 9.6 register overview name w/r addr43210default 1) 1) the default values are set after reset. out w/r 00 b out4 out3 out2 out1 out0 00 h hwcr r 10 b rst x sbm pwm ctl 00 h w10 b rst 0 0 pwm ctl 00 h dcr w/r 11 b 00 mux 07 h
spi power controller spoc - BTS5566G application description data sheet 38 rev. 1.3, 2007-10-30 10 application description figure 23 application circuit example c vss spi vbb limp home lhi gnd out3 out2 out1 out0 out4 gnd vbb lh i vcc v bat ad 2k ? 2k ? 2k ? 2k ? 5v vdd vdd 100nf 500 ? lh i 8k ? 8k ? 3. 3k ? 1k ? 1nf gpio gpio so sclk si cs is in1 in2 in3 in4 in0 circuit .emf spi 8k ? 10nf. . 100nf 68nf schottky 27w 27w 27w 10w 10w
data sheet 39 rev. 1.3, 2007-10-30 spi power controller spoc - BTS5566G package outlines spoc - BTS5566G 11 package outlines spoc - BTS5566G figure 24 pg-dso-36-34 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps01089 2) does not include dambar protrusion of 0.05 max. per side 1) does not include plastic or metal protrusion of 0.15 max. per side 1 18 36 19 0.65 0.33 0.2 2.45 2.65 max. 0.1 -0.2 -0.1 0.23 +0.09 0.35 x 45? -0.2 1) 7.6 10.3 0.7 ?.2 8? max. ?.3 index marking 1) 12.8 -0.2 18 1 19 36 index marking ejector mark bottom view 0.17 m c a-b d 36x ?.08 2) c d a b you can find all of our packages, sorts of pa cking and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
spi power controller spoc - BTS5566G revision history data sheet 40 rev. 1.3, 2007-10-30 12 revision history revision date changes 1.3 07-10-30 ? chapter 11 package outline drawing changed 1.2 07-08-28 ? 4.1 conditions updated ? 4.1 and 6.4 : footnote change to : specified r thja value is according to jedec jesd51- 2,-5,-7 at natural convecti on on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). ? 4.1.4 conditions updated ? 4.1.28 definition change ? 5.2 reset command : t cs(td) change to : t cs(td) . ? 8.4.1 kilis : updated values for channel 2-3 ? 8.4.3 new parameter : current sense leakage / offset current ? max input voltage value change to 40 volts 1.1 07-03-05 ? product summary green product (rohs compliant) and aec qualified added ? 4.1.12 current through input pins min value change to -0.75ma ? 4.1.21 current through limp home input pin min value change to -0.75ma ? chapter 2 test pin change to vbb ? chapter 6 r on definition changed ? chapter 7.2 (also even in case of v dd = 0v) added. ? basic feature : green logo added ? chapter 8.1 in case of high du ty cyle ( off state of output < t off state_min ) the v ds might not be equal to v bb during the off state of the power mosfet. the over load monitoring signals might be set and latc hed in the error flags. see application note ? software strategy for diagnosis during pwm-operation? for more details ? table 8.4.10 off statetime duri ng pwm operation definition ? chapter 11 68nf added between v bb and gnd ? page 18: register read value added ? new template din a4 v1.2
edition 2007-10-30 published by infineon technologies ag 81726 munich, germany ? infineon technologies ag 2007. all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the app lication of the device, infi neon technologies hereby disclaims any and all warranties a nd liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
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